Much attention is given to certain aspects of integrated circuit (IC) technology, such as the number or dimensions of the devices in the circuit and circuit processing speeds that can reach millions of instructions per second (MIPS). Clearly, progress in these areas has great appeal and is readily understood. However, there are other aspects of very large scale integrated (VLSI) circuit technology that are of significant importance. For example, the various devices, e.g., sources, gates and drains, of the integrated circuits must be electrically connected to be of any use within a larger electrical circuit. In the prior art, active devices have been successfully connected by depositing patterned metal, usually aluminum but more recently copper, in one or more layers above the device layers. To interconnect the appropriate devices and metal layers, metal plugs, typically tungsten (W) are formed through the dielectric layers and between the different metal layers. Significantly, the metal layering process is much more expensive than other processes such as ion implantation. The methods for defining and forming such patterned metal layers tungsten plugs, and dielectric layers are well known to those who are skilled in the art.
Market demands for faster and more powerful integrated circuits have resulted in significant growth in the number of devices per cm.sup.2, i.e., a higher packing fraction of active devices. This increased packing fraction invariably means that the interconnections for ever-more-complicated circuits are made to smaller dimensions than before. However, as device sizes reach 0.25 .mu.m and below, physical limitations of the metal deposition processes prevent reducing the scale of the device interconnections at the same rate as the devices.
Accordingly, what is needed in the art is a method for forming semiconductor device interconnections that is more cost effective and is not size limited as in the prior art. The present invention addresses this need.